Senior RTL Design Engineer (Hybrid) – PCIe/CXL VIP
Siemens AG
Location Not Specified
Posted
💰$125 – $150/hr
Senior Level
Job Description
A leading global technology firm is looking for an experienced software developer in Austin to develop vital verification IPs for advanced electronic design automation.
The candidate must have at least 15 years of experience in RTL design and IP verification.
Strong knowledge of SystemVerilog, bus protocols, and the ability to engage directly with customers is essential.
We offer a comprehensive benefits package along with a competitive salary and a hybrid work environment.#J-18808-Ljbffr