Senior Chip Design Engineer

AWS Utility Computing (UC) provides product innovations — from foundational services such as Amazon’s Simple Storage Service (S3) and Amazon Elastic Compute Cloud (EC2), to consistently released new product innovations that continue to set AWS’s services and features apart in the industry. As a member of the UC organization, you’ll support the development and management of Compute, Database, Storage, Internet of Things (IoT), Platform, and Productivity Apps services in AWS, including support for customers who require specialized security solutions for their cloud services.

Take part in the development of cutting-edge products within a disruptive system architecture. You will have the opportunity to work on the technologies that power the world’s largest cloud provider, in a dynamic, open, and fast-paced environment. AWS provides a highly reliable, scalable, low-cost infrastructure platform in the cloud, which powers hundreds of thousands of businesses in 190 countries around the world. Annapurna Labs, as part of Amazon Web Services (AWS), is looking for talented engineers to help us develop a semiconductor platform based on a revolutionary architecture.

Looking for exceptional senior engineers to join the top-tier team that is developing the next generation semiconductor platform, based on a revolutionary architecture. Engineers will participate in design and verification activities, working on the next generation of our products.

You are invited to take part in developing, integrating and deploying cutting-edge technologies, starting with identification and definition of project requirements, architecture, feature development, and collaboration with the different groups. Your design will be integrated into the nitro SoC, on millions of servers worldwide. This is an opportunity to have a large-scale impact.

As a VLSI engineer and a member of the Nitro project, you will have an impact over the device through its entire lifecycle, from the product definition stage to mass production. You will work in close collaboration with multiple groups, including Architecture, Software, Verification, Backend, and DFT.

Key job responsibilities

1. Full ownership of one or more IPs within the product:
1. Micro-architecture
2. RTL coding and debug
3. Synthesis and timing closure
4. Sign-off
2. Supporting the Verification and Emulation teams: Test plan, Coverage review
3. Ensuring that the chip meets quality and reliability standards
4. Collaborating with cross-functional teams, including Product Definition, Verification, Software, and Physical design

Minimum Requirements

1. 6+ years of experience in chip design
2. Verilog / System Verilog
3. Fluent with Scripting (C* / Perl / Python/ TCL)
4. BSc in Electrical Engineering/Computer Engineering/Computer Science
5. Protocols: AXI, CHI, DDR, Networking, PCIe
6. Architecture of NOC, Coherent and non-Coherent fabrics
7. Experience with the entire SoC cycle – Synthesis / STA / CDC / Lint
8. Experience with Design Automation.
9. Higher degree in a related technical field is an advantage.

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