Senior Staff Engineer, NPI Packaging R&D

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Location:
San Diego, CA, US

pSemi Corporation is a Murata company driving semiconductor integration. pSemi builds on Peregrine Semiconductor’s 30-year legacy of technology advancements and strong IP portfolio but with a new mission—to enhance Murata’s world-class capabilities with high-performance semiconductors. With a strong foundation in RF integration, pSemi’s product portfolio now spans power management, connected sensors, optical transceivers, antenna tuning and RF frontends. These intelligent and efficient semiconductors enable advanced modules for smartphones, base stations, personal computers, electric vehicles, data centers, IoT devices and healthcare. From headquarters in San Diego and offices around the world, pSemi’s team explores new ways to make electronics for the connected world smaller, thinner, faster and better.

Position Summary:

We are seeking an experienced Senior Staff Engineer to lead semiconductor packaging innovations through all phases of product development. This role will focus heavily on mechanical design and the use of Finite Element Analysis (FEA) to ensure the integrity and performance of packaging solutions for high-volume, high-reliability applications across industrial, commercial, and automotive sectors. The ideal candidate will have extensive hands-on experience with semiconductor packaging technologies, as well as expertise in product qualification, process development, and team leadership.

Key Responsibilities:

1. Mechanical Design & FEA Expertise: Lead the mechanical design of new products with consideration of bump and package assembly processes using FEA tools (such as Ansys).
2. Technology Leadership: Develop and maintain industry best design practices for data interoperability across CAD and Product Life Cycle management systems.
3. Cross-Functional Leadership: Guide cross-functional teams in making critical mechanical decisions throughout the product development stages.
4. Process Development & Risk Mitigation: Define and develop manufacturing processes by performing detailed design analysis (tolerance analysis, FEA, etc.) and guiding risk assessments.
5. Technology Development & Supplier Engagement: Mechanical CAD tool owner collaborating with suppliers and other design tool owners to drive innovation in a competitive market.
6. Design Documentation & Oversight: Coordinate preparation of design documentation, BOM, and assembly process flows, ensuring all aspects meet technical specifications and quality standards.
7. Team Mentorship: Mentor junior engineers and lead technical development efforts across packaging and assembly disciplines.
8. Failure Analysis & Problem Resolution: Root cause analysis and resolution of issues during both the development and production phases.

Minimum Qualifications:

1. Education: Bachelor’s degree in Engineering (Mechanical, Electrical, Packaging, Materials, or Chemical), Physics, or Chemistry. MS preferred.
2. Experience: At least 12 years in electronics packaging, including 5 years of hands-on experience in specific packaging technologies.
3. Mechanical & FEA Expertise: Demonstrated experience in FEA, package design, and development, particularly in high-reliability, high-volume products.
4. Design & Development Tools: Proficient with tools such as AutoCAD, Cadence Allegro, and FEA tools (Ansys).
5. Packaging Knowledge: In-depth understanding of microelectronic packaging technologies, including flip chip bumping, wafer backend processing, and SMT.
6. Cross-Functional Team Leadership: Experience leading cross-functional teams in a fast-paced, deadline-driven environment.
7. Process & Risk Management: Ability to assess design feasibility, conduct cost-risk analysis, and mitigate technical risks during product development.

Preferred Qualifications:

1. RF Product Design: Experience with the design and packaging of RF products.
2. Statistical Analysis Tools: Familiarity with statistical software or tools for analysis.
3. Automated Task Management: Experience with Excel macros or automation for process optimization.
4. PCB Fabrication: Understanding of PCB fabrication and design processes.
5. Package Reliability & Quality Assurance: Knowledge of semiconductor quality and reliability standards and failure modes.

USD $172,201.96 - $223,874.95 per year

pSemi Corporation supports a diverse workforce and is committed to a policy of equal employment opportunity for applicants and employees. pSemi does not discriminate on the basis of age, race, color, religion (including religious dress and grooming practices), sex/gender (including pregnancy, childbirth, or related medical conditions or breastfeeding), gender identity, gender expression, genetic information, national origin (including language use restrictions and possession of a driver’s license issued under Vehicle Code section 12801.9), ancestry, physical or mental disability, legally-protected medical condition, military or veteran status (including “protected veterans” under applicable affirmative action laws), marital status, sexual orientation, or any other basis protected by local, state or federal laws applicable to the Company. pSemi also prohibits discrimination based on the perception that an employee or applicant has any of those characteristics, or is associated with a person who has or is perceived as having any of those characteristics.

Note: The Peregrine Semiconductor name, Peregrine Semiconductor logo and UltraCMOS are registered trademarks and the pSemi name, pSemi logo, HaRP and DuNE are trademarks of pSemi Corporation in the U.S. and other countries. All other trademarks are the property of their respective companies. pSemi products are protected under one or more of the following U.S. Patents: