Principal FPGA Design Engineer

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware, and IP that turn design concepts into reality. Cadence customers are the world's most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace, industrial, and health.

The Cadence Advantage

• The opportunity to work on cutting-edge technology in an environment that encourages creativity, innovation, and making an impact.
• Employee-friendly policies focusing on physical and mental well-being, career development, learning opportunities, and recognition of employee needs.
• The "One Cadence - One Team" culture promotes collaboration within and across teams to ensure customer success.
• Multiple avenues for learning and development tailored to individual interests and requirements.
• Work with a diverse team of passionate, dedicated, and talented individuals committed to exceeding expectations for customers, communities, and colleagues.

Job Responsibilities

Protium is a leading product in FPGA Emulation / Prototyping. This role involves designing, verifying, ensuring timing closure, and hardware validating FPGA IPs.

• Develop FPGA IPs for the Protium platform, including design, verification, integration, timing closure, documentation, and release to end users.
• Design, verify, simulate, perform timing closure, and validate FPGA IPs on hardware.
• Enhance existing IPs and develop new ones.
• Debug and resolve internal regression failures related to FPGA IPs.
• Document FPGA IPs thoroughly.

Position Requirements / Qualifications

• Master's degree in Electrical Engineering with 5+ years of experience.
• Proficiency in FPGA design and verification using Verilog.
• Experience with high-end Xilinx (AMD) FPGAs and the Vivado tool for simulation, placement, and routing.
• Hands-on experience debugging FPGAs using Vivado hardware manager, firmware, and software.
• Proficiency with Linux servers and scripting using Shell, Perl, or TCL.
• Experience with Cadence simulators Incisive or Xcelium.
• Detailed knowledge of industry-standard interfaces such as PCI Express, DRAM / DDR4, SRAM, I2C, JTAG, and AXI.

The annual salary range for California is $131,600 to $244,400, with potential incentive compensation including bonuses, equity, and benefits. Sales roles typically offer a competitive On Target Earnings (OTE) incentive structure. Compensation varies based on qualifications, skills, competencies, and location. Benefits include paid vacation and holidays, 401(k) with employer match, employee stock purchase plan, and various medical, dental, and vision options.

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